CALL FOR PAPERS

ISLPED'04
INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN



Executive Committee and Symposium Officers

General Co-Chairs:

Rajiv Joshi
IBM
rvjoshi@us.ibm.com
                   
Kiyoung Choi
Seoul National University
kchoi@azalea.snu.ac.kr

Program Co-Chairs:

Kaushik Roy
Purdue University
kaushik@ecn.purdue.edu

Vivek Tiwari
Intel
Vivek.tiwari@intel.com

Treasurer:

Vijay Narayanan
Penn State University
vijay@cse.psu.edu

Publicity Chairs:

Mahmut Kandemir
Penn. State
Jihong Kim (Asian publicity)
Seoul Natl. Univ.
kandemir@cse.psu.edu
jihong@davinci.snu.ac.kr

Local Arrangements Chair:

Payam Heydari
UC-Irvine
payam@ece.uci.edu

Design Contest Chair:

David Scott
Texas Instruments
david.scott@ti.com

Exhibits Chair:

Diana Marculescu
Carnegie Mellon University
dianam@ece.cmu.edu

Other Members of the EC:

B. Barton, Texas Instruments
D. Blaauw, Univ. of Michigan
R. Brodersen, UC Berkeley
A. Chandrakasan, MIT
E. Cheng, Synopsys
J. Cong, UCLA
V. De, Intel Corporation
G. DeMicheli, Stanford
C. Enz, CSEM
M. J. Irwin, Penn State Univ.
E. Macii, Poli di Torino
F. Najm, University of Toronto
I. Verbauwhede, UCLA
M. Pedram, USC
C. Piguet, CSEM
J. Rabaey, UC Berkeley
T. Sakurai, Univ. of Tokyo

Sponsored by ACM SIGDA and IEEE Circuits and Systems Society with technical co-sponsorship from the IEEE Solid-State Circuits Society and the IEEE Electron Devices Society.

The International Symposium on Low Power Electronics and Design (ISLPED) is the premier forum for presentation of recent advances in all aspects of low power design and technologies, ranging from process and circuit technologies, to simulation and synthesis tools, to system level design and optimization. Specific topics include, but are not limited to, the following two main areas, each with three sub-areas:


1. Architecture, Circuits, and Technology
2. Design Tools, System and Software Design

1.1. Technologies and Digital Circuits
   Emerging logic and memopry technologies, Device design, Low power low leakage circuits, Memory circuits, Cooling technologies, Battery technologies

2.1. Design Tools
       Energy simulation and estimation tools that operate at the circuit/gate level, RT level, behavioral level, and algorithmic level, Physical design and interconnects

1.2. Logic and Microarchitecture Design
 Processor core design, Cache design, Logic and RTL design, Arithmetic and signal processing circuits, Encryption technologies, Asynchronous design

2.2. System Design and Methodologies
      Microprocessor, DSP and embedded systems design, FPGA and ASIC designs ,  System level power management, Behavioral and system level design aids

1.3. Analog, MEMS and Mixed Signal Electronics
       RF circuits, Wireless, MEMS circuits, AD/DA Converters, Mixed-signal circuits, DC-DC conversion
2.3. Software Design and Optimization
       Power aware compiler and operating system design, Application level optimizations, Wireless and sensor networks

Submissions on new, emerging topics are particularly encouraged.


REVISED TECHNICAL PAPER SUBMISSIONS DEADLINE:  Full papers should be received by February 20, 2004

Submissions should be full-length papers of up to 6 pages (double-column format, font size 9pt to 10pt), including all illustrations, tables, references and an abstract of no more than 100 words, but excluding the authors' names and affiliations. Papers in the wrong fromat, exceeding the six-page limit or identifying authors or their affiliations will not be reviewed.

Electronic submission in pdf format only via the web is required. At most one resubmission (of a revised version of a previously submitted paper) will be allowed.  More information on electronic submission to ISLPED'04 can be found at http://www.islped.org.

Submitted papers must describe original work that will not be announced or published prior to the Symposium and that is not being considered or under review by another conference at the same time. Accepted papers will be presented in one of two parallel tracks: one focusing on architectures, circuits and technologies, the other on design tools and systems and software design for low power. Notification of paper acceptance will be mailed by April 23, 2004 and the camera-ready version of the paper will be due by May 24, 2004. Accepted papers will be published in the Symposium Proceedings and included in the annual ACM SIGDA CD-ROM Publication Compendium.


INVITED TALK, PANEL, AND TUTORIAL PROPOSALS DEADLINE: RECEIVED by March 15, 2004.

There will be several invited talks by industry and academic leaders on key issues in low power electronics and design. All invited talks will be in plenary sessions. The Symposium also may include embedded tutorials to provide attendees with the necessary background to follow recent research results as well as an evening panel on future directions and design/technology alternatives in low power electronics and design. Proposals for invited talks, embedded tutorials, and the panel should be sent to:


 Kaushik Roy                                                                                                                              Vivek Tiwari
 Electrical & Computer Engineering                                                                                           Intel Corporation
 Purdue University                                                                                                                        Santa Clara
 West Lafayette, IN 47907                                                                                                            California
 kaushik@ecn.purdue.edu                                                                                                     vivek.tiwari@intel.com



Companies interested in exhibiting at the Symposium should contact the Exhibits Chair by June 25, 2004.