ISLPED 2026

See the keynotes page for full abstracts and speaker bios.

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  Day 1 · Wednesday, August 5

  Naveen Verma

  Ralph H. and Freda I. Augustine Professor of Electrical and Computer Engineering · Co-Founder & CEO of EnCharge AI

  Princeton University · EnCharge AI

  In-Memory Computing for Next-Generation AI: low-power design applied to a new era of circuits and architectures

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  Most deployments of AI will be power limited, because its usefulness is driving more AI across platforms, from the Edge to the Data Center. The efficiency gap is so acute, that transformative circuits and architectures will be required. This, in turn, drives a critical evolution in how we think about low-power systems design. This talk focuses on the approach of in-memory computing (IMC), which has gained a high level of interest, due to its ability to solve the two-sided problem of arithmetic efficiency and data-movement. This talk surveys the major findings and lessons learned as the industry moves towards this transformative technology, particularly based on analog operation. The insights start at the level of fundamental tradeoffs, and drive essential implications at the device, circuit, architectural, and algorithmic levels. Specifically focusing on practical architectures for delivering scaled-up system-level efficiency inflections brings to the forefront critical challenges for many analog pathways, while illuminating approaches that can and are driving large efficiency boosts, as prevailing digital trajectories are saturating. As we think about these, it is also essential to consider how such inflections can be constructively adopted in increasingly complex and multi-faceted ecosystem and system requirements, and not break the way systems are constructed today and in the future. This requires considering architectural and software design approaches, as well as alignments with key industrial trends.

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  Day 2 · Thursday, August 6

  Wilfred G. van der Wiel

  Professor of Nanoelectronics · Co-Director, BRAINS Center for Brain-Inspired Computing

  University of Twente · University of Münster

  Reconfigurable Nonlinear Computing in Silicon

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  Most AI hardware accelerates linear operations, in particular matrix-vector multiplications. However, neural networks derive much of their expressive power from nonlinear transformations. This motivates hardware that performs nonlinear processing directly in physical devices. In this talk, I will discuss reconfigurable nonlinear-processing units (RNPUs): silicon-based, multi-terminal nanoelectronic devices with tunable nonlinear input-output characteristics. By exploiting device physics for computation, RNPUs can perform analogue nonlinear transformations locally, reducing data movement, circuit overhead and power consumption. I will highlight recent results on RNPUs, including analogue speech recognition, physical Kolmogorov-Arnold Networks, and the space-charge mechanism underlying the strong nonlinear response. Together, these results point toward a CMOS-compatible route to compact, low-latency and energy-efficient AI hardware.

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  Day 3 · Friday, August 7

  Hoshik Kim

  Senior Vice President and Fellow, Memory Systems Research

  SK hynix Inc.

  Near-Data Computing: The Energy Imperative

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  As AI scales, both industry and academia have long pursued near-data processing as a path to major performance gains. Today, performance is no longer the only challenge—energy is the real bottleneck. Data movement now consumes orders of magnitude more energy than computation itself, making traditional architectures increasingly unsustainable for next-generation AI data centers as well as battery-constrained edge devices. In this new energy-limited computing era, near-data processing has moved from an intriguing idea to a practical necessity. Approaches span in-sensor, in-memory, in-storage, and in-network processing, depending on where data is created and resides. Among them, near-memory processing is rapidly becoming reality. This talk explores the shift toward tightly integrated compute-memory systems, including 3D architectures that dramatically cut data movement and energy use. I expect we will see more domain-specific architectures and heterogeneous systems built around that idea. It's really a move toward a memory-centric design for AI infrastructure.