Keynotes
Monday Keynote:
Hsien-Hsin Sean Lee AI Infrastructure Research Head |
The Computing Frontiers of Social Network Monday, July 29, 9:00~10:00am |
Abstract:
Biography:Social networks have been deeply woven into our everyday life. These platforms provide a real-time venue with many functions that keep people connected, deliver useful/customized services, and maintain information transparency. Underneath their infrastructure, the adoption of AI/machine learning (ML) mechanisms are becoming omnipresent in datacenters, steering a variety of services to enhance the effectiveness of users’ communication and to improve the quality of online experiences. Meanwhile, ML could consume enormous computing resources to achieve these objectives and require meticulous resource provisioning and management. In this talk, I will share Facebook's perspectives on the novel challenges as well as their implication to modern technologies and the impact to the end-to-end system designs for social network computing. In addition, I will discuss our open-source endeavor such as Caffe2/PyTorch and our joint effort with other ML enthusiasts in standardizing ML benchmarks for the global research community.
Hsien-Hsin Sean Lee leads the AI Infrastructure Research group at Facebook Boston. Previously, he directed the EDA design flow solutions and oversaw the entire PDK development for IC design customers at Taiwan Semiconductor Manufacturing Company (TSMC), Taiwan. Prior to TSMC, he was a tenured Associate Professor at the School of Electrical and Computer Engineering, Georgia Tech at Atlanta for 10 years and spent six years as a senior CPU architect at Intel Corporation. Dr. Lee holds a Ph.D. in Computer Science and Engineering from the University of Michigan at Ann Arbor. He received National Awards including the NSF CAREER Award and the Department of Energy Early CAREER Award. He has published two book chapters and more than 100 technical articles including 4 Best Paper Awards. While at Georgia Tech, his team demonstrated one of the first 3D die-stacked many-core chips (3D-MAPS) in ISSCC 2012. He served as an Associate Editor of IEEE Trans. on CAD, IEEE Trans. on Computers, ACM Trans. on Architecture and Code Optimization, and IEEE MICRO Magazine. He also served as the General Chair for IISWC 2010, the Program Co-Chair for MICRO 2016, an Executive Committee Member for IEEE-TCCA, an Industry Advisory Board Member for IEEE Computer Society and a TPC Member for more than 90 international conferences. Dr. Lee holds 24 US patents and is a Fellow of the IEEE.
Tuesday Keynote:
Prof. Luca Benini Professor ETH Zurich, Switzerland |
Extreme Edge AI - The Parallel Ultra-low Power (PULP) Approach Tuesday, July 30, 9:00~10:00am |
Abstract:
Biography:Edge Artificial Intelligence (AI) is the new mega-trend, as privacy concerns and networks bandwidth/latency bottlenecks prevent cloud offloading of AI functions in many application domains, from autonomous driving to advanced prosthetics and sub-watch wearables. Hence we need to push AI functionality toward sensors and actuators, and comply with the ensuing low-power low cost requirements. In this talk I will give an overview of our recent efforts in developing systems of-on-chips capable of significant analytics and AI functions "at the extreme edge", i.e. within the limited power budget of traditional microcontrollers that can be co-located and integrated in-module or in-package with the sensors themselves. These "extreme edge AI" platforms enable major business opportunities in many application domains and create a exciting playground for low power digital and mixed-signal design.
Luca Benini holds the chair of digital Circuits and systems at ETHZ and is Full Professor at the Universita di Bologna. He received a PhD from Stanford University. In 2009-2012 he served as chief architect in STmicroelectronics France. Dr. Benini's research interests are in energy-efficient computing systems design, from embedded to high-performance. He is also active in the design ultra-low power VLSI Circuits and smart sensing micro-systems. He has published more than 1000 peer-reviewed papers and five books. He is an ERC-advanced grant winner, a Fellow of the IEEE, of the ACM and a member of the Academia Europaea. He is the recipient of the 2016 IEEE CAS Mac Van Valkenburg award and of the 2019 IEEE TCAD Donald O. Pederson Best Paper Award.
Wednesday Keynote:
Prof. Giovanni De Micheli Professor, Head of EE Institute EPFL |
Nanosystems: Technology and Tools Wednesday, July 31, 9:00~10:00am |
Abstract:
Biography:Integrated nanosystems design requires a good match of technologies and tools. I will first present the landscape of emerging technologies and in particular enhanced-functionality devices exploiting new materials and geometries as well as their application into circuits, Then, I will focus on new methods for synthesis of integrated circuits based on majority algebra and I will conclude by presenting results from experimental design tools.
Giovanni De Micheli is Professor and Director of the Institute of Electrical Engineering at EPFL Lausanne, Switzerland. He is program leader of the Nano-Tera.ch program. Previously, he was Professor of Electrical Engineering at Stanford University.He holds a Nuclear Engineer degree (Politecnico di Milano, 1979), a M.S. and a Ph.D. degree in Electrical Engineering and Computer Science (University of California at Berkeley, 1980 and 1983).
Prof. De Micheli is a Fellow of ACM and IEEE, a member of the Academia Europaea and an International Honorary member of the American Academy of Arts and Sciences. His research interests include several aspects of design technologies for integrated circuits and systems, such as synthesis for emerging technologies, networks on chips and 3D integration. He is also interested in heterogeneous platform design including electrical components and biosensors, as well as in data processing of biomedical information. He is author of: Synthesis and Optimization of Digital Circuits, McGraw-Hill, 1994, co-author and/or co-editor of nine other books and of over 850 technical articles. His citation h-index is 95 according to Google Scholar. He is member of the Scientific Advisory Board of IMEC (Leuven, B), CfAED (Dresden, D) and STMicroelectronics.
Prof. De Micheli is the recipient of the 2016 IEEE/CS Harry Goode award for seminal contributions to design and design tools of Networks on Chips, the 2016 EDAA Lifetime Achievement Award, the 2012 IEEE/CAS Mac Van Valkenburg award for contributions to theory, practice and experimentation in design methods and tools and the 2003 IEEE Emanuel Piore Award for contributions to computer-aided synthesis of digital systems. He received also the Golden Jubilee Medal for outstanding contributions to the IEEE CAS Society in 2000, the D. Pederson Award for the best paper on the IEEE Transactions on CAD/ICAS in 1987 and 2018, and several Best Paper Awards, including DAC (1983 and 1993), DATE (2005), Nanoarch (2010 and 2012) and Mobihealth(2016).