Preliminary Program
Papers Accepted for Oral Presentation
- • 11 Energy-Efficient Dynamic Comparator with Active Inductor for Receiver of Memory Interfaces
- • 14 RMAC: Runtime Configurable Floating Point Multiplier for Approximate Computing
- • 16 App-Oriented Thermal Management of Mobile Devices
- • 24 Aggressive Slack Recycling via Transparent Pipelines
- • 25 Blacklist Core: Machine-Learning Based Dynamic Operating-Performance-Point Blacklisting for Mitigating Power-Management Security Attacks
- • 37 TrainWare: A Memory Optimized Weight Update Architecture for On-Device Convolutional Neural Network Training
- • 44 Load-Triggered Warp Approximation on GPU
- • 46 Enabling Intra-Plane Parallel Block Erase in NAND Flash to Alleviate the Impact of Garbage Collection
- • 54 Multiple Combined Write-Read Peripheral Assists in 6T FinFET SRAMs for Low-VMIN IoT and Cognitive Applications
- • 65 4-Channel Push-Pull VCSEL Drivers for HDMI Active Optical Cable in 0.18-um CMOS
- • 70 Pareto-Optimal Power- and Cache-Aware Task Mapping for Many-Cores with Distributed Shared Last Level Cache
- • 71 GAS: A Heterogeneous Memory Acceleration for Graph Processing
- • 78 Enhancing the Energy Efficiency of Journaling File System via Exploiting Multi-Write Modes on MLC NVRAM
- • 80 HomeRun: HW/SW Co-Design for Program Atomicity on Self-Powered Intermittent Systems
- • 81 Value-driven Synthesis for Neural Network ASICs
- • 84 SPONGE: A Scalable Pivot-based On/Off Gating Engine for Reducing Static Power in NoC Routers
- • 87 Road to High-Performance 3D ICs: Performance Optimization Methodologies for Monolithic 3D ICs
- • 99 CLINK: Compact LSTM Inference Kernel for Energy Efficient Neurofeedback Devices
- • 103 Designing Efficient Imprecise Adders using Multi-bit Approximate Building Blocks
- • 106 Compact Convolution Mapping on Neuromorphic Hardware using Axonal Delay
- • 112 Computing in memory with FeFETs
- • 115 Threshold Defined Camouflaged Gates in 65nm Technology for Reverse Engineering Protection
- • 119 Reliability and Uniformity Enhancement in 8T-SRAM based PUFs operating at NTC
- • 120 AxTrain: Hardware-Oriented Neural Network Training for Approximate Inference
- • 127 ACE-GPU: Tackling Choke Point Induced Performance Bottlenecks in a Near-Threshold Computing GPU
- • 130 A Monolithic-3D SRAM Design with Enhanced Robustness and In-Memory Computation Support
- • 131 Efficient and Secure Group Key Management in IoT using Multistage Interconnected PUF
- • 137 NNest: Early-Stage Design Space Exploration Tool for Neural Network Inference Accelerators
- • 142 A Miniature Self-Powered Inertial Sensor Node Based on Bluetooth Low Energy
- • 146 Fault Injection and Information Leakage Attacks on Non-Volatile Memory
- • 156 An Energy-Efficient, Yet Highly-Accurate, Approximate Non-Iterative Divider
- • 167 An Energy-Efficient High-Swing PAM-4 Voltage-Mode Transmitter
- • 170 DiReCt: Resource-Aware Dynamic Model Reconfiguration for Convolutional Neural Network in Mobile Systems
- • 172 Dual Mode Ferroelectric Transistor based Non-Volatile Flip-Flops for Intermittently Powered Systems
- • 184 Spin Orbit Toque Device based Stochastic Multi-bit Synapses for On-chip STDP Learning
Papers Accepted for Poster Presentation
- • 31 A Low-power 4096x2160@30fps H.265/HEVC Video Encoder for Smart Video Surveillance
- • 35 Input-Splitting of Large Neural Networks for Power-Efficient Accelerator with Resistive Crossbar Memory Array
- • 42 Design Optimization of 3D MPSoCs with Integrated Flow Cell Arrays
- • 62 Multi-Pattern Active Cell Balancing Architecture and Equalization Strategy for Battery Packs
- • 82 Intrinsic and Database-free Watermarking in ICs by Exploiting Process and Design Dependent Variability in Metal-Oxide-Metal Capacitances
- • 88 Scheduling of Hybrid Battery-Supercapacitor Control Instructions for Longevity in Systems with Power Gating
- • 90 Better-Than-Worst-Case Design Methodology for a Compact Integrated Switched-Capacitor DC-DC Converter
- • 107 Dynamic Bitwidth Re-Configuration for Energy Efficient Deep Learning Hardware
- • 118 Lop: An Open-Source Library for Customized Data Representation and Approximate Computing Targeting Energy and Resource Utilization Efficiencies in Deep Neural Networks
- • 124 Breaking POps/J Barrier with Analog Multiplier Circuits Based on Nonvolatile Memories
- • 128 Battery-Aware Energy Model of Drone Delivery Tasks
- • 147 A Fully Onchip Binarized Convolutional Neural Network FPGA Implementation with Accurate Inference
- • 154 In-situ Stochastic Training of MTJ Crossbar based Neural Networks
- • 157 Variation-Aware Pipelined Cores through Path Shaping and Dynamic Cycle Adjustment: Case Study on a Floating-Point Unit
- • 171 Efficient Image Sensor Subsampling for DNN-Based Image Classification
- • 179 A 2.6 mW Single-Ended Positive Feedback LNA